1. Field of the Invention
The present invention relates to a nonvolatile memory device with multiple references and to a control method thereof.
2. Description of the Related Art
It is known that reading nonvolatile memory cells, for example of an EEPROM or Flash type, may cause undesirable phenomena of spurious programming (referred to also as “read disturb”). With reference to FIG. 1, a nonvolatile memory cell 1 comprises: a source region 2 and a drain region 3, both formed in a semiconductor substrate 4 and respectively provided with a source terminal 1a and a drain terminal 1b; a channel region 5, extending in the substrate 4 between the source region 2 and the drain region 3; a floating-gate region 6, separated from the channel region 5 by a tunnel-oxide layer 7; and a control-gate region 8, which is in turn separated from the floating-gate region 6 by an insulating layer 9 and is provided with a gate terminal 1c. During read or verify operations, an electric field E is set up between the floating-gate region 6 and the substrate 4 (in particular, the channel region 5). Said electric field E is necessary to enable passage of current between the source region 2 and the drain region 3. However, a mechanism altogether similar to that of programming causes a fraction of the electrons traveling in the channel region 5 to be deviated and trapped in the floating-gate region 6, thus altering the threshold voltage of the cell 1. The phenomenon of spurious programming is all the more effective the lower the threshold voltage of the cell 1 (since the electric field E is greater) and regards above all the cells used as reference for the read operations, program-verify operations, erase-verify operations, and depletion-verify operations. In fact, whereas the array cells are randomly selected for reading/programming, the reference cells are systematically used at every access to the memory. Consequently, the reference cells are read a number of times that is greater by some orders of magnitude than the average number of accesses to the individual array cell.
In practice, two harmful effects occur. The first, illustrated in FIGS. 2a and 2b in the case of a four-level (two-bit) cell, regards the reduction in the distance that separates the ranges of threshold voltages associated to the various levels (designated by VT1, VT2, VT3 and VT4) and between the references (the read references, the program-verify references, the erase-verify reference, and the depletion-verify reference, are designated, respectively, by VR1, VR2, VR3, by VP1, VP2, VP3, by VE, and by VD). In fact, the cells having a lower threshold voltage are subject to a more intense drift, due to spurious programming, and hence, with time, the reference ranges and levels tend to be compressed (FIG. 2b) as compared to an initial situation (FIG. 2a). The number of reading errors consequently tends to increase, even following upon modest disturbance.
The second effect, which is more serious, depends upon the higher reading frequency of the reference cells and is illustrated in FIGS. 2a and 2c. The drift in the threshold voltages of the reference cells, in fact, is faster as compared to that of the array cells. Consequently, with respect to the initial situation of FIG. 2a, the threshold voltages of the reference cells can overlap the intervals associated to the levels admissible for the array cells. In this case, systematic reading errors arise.
Even though the one-bit cells also suffer from the problem described above, said problem is much more serious in multilevel memories, because the levels are closer to one another and the margins narrow.